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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/mips/mips32-dsp/multu.c
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/mips/mips32-dsp/multu.c')
-rw-r--r--qemu/tests/tcg/mips/mips32-dsp/multu.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/qemu/tests/tcg/mips/mips32-dsp/multu.c b/qemu/tests/tcg/mips/mips32-dsp/multu.c
new file mode 100644
index 000000000..85d36c1b6
--- /dev/null
+++ b/qemu/tests/tcg/mips/mips32-dsp/multu.c
@@ -0,0 +1,24 @@
+#include<stdio.h>
+#include<assert.h>
+
+int main()
+{
+ int rs, rt, ach, acl;
+ int result, resulth, resultl;
+
+ rs = 0x00FFBBAA;
+ rt = 0x4B231000;
+ resulth = 0x4b0f01;
+ resultl = 0x71f8a000;
+ __asm
+ ("multu $ac1, %2, %3\n\t"
+ "mfhi %0, $ac1\n\t"
+ "mflo %1, $ac1\n\t"
+ : "=r"(ach), "=r"(acl)
+ : "r"(rs), "r"(rt)
+ );
+ assert(ach == resulth);
+ assert(acl == resultl);
+
+ return 0;
+}