diff options
author | Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
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committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/mips/mips32-dsp/insv.c | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/mips/mips32-dsp/insv.c')
-rw-r--r-- | qemu/tests/tcg/mips/mips32-dsp/insv.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/qemu/tests/tcg/mips/mips32-dsp/insv.c b/qemu/tests/tcg/mips/mips32-dsp/insv.c new file mode 100644 index 000000000..9d674697c --- /dev/null +++ b/qemu/tests/tcg/mips/mips32-dsp/insv.c @@ -0,0 +1,36 @@ +#include<stdio.h> +#include<assert.h> + +int main() +{ + int rt, rs, dsp; + int result; + + /* msb = 10, lsb = 5 */ + dsp = 0x305; + rt = 0x12345678; + rs = 0x87654321; + result = 0x12345438; + __asm + ("wrdsp %2, 0x03\n\t" + "insv %0, %1\n\t" + : "+r"(rt) + : "r"(rs), "r"(dsp) + ); + assert(rt == result); + + dsp = 0x1000; + rt = 0xF0F0F0F0; + rs = 0xA5A5A5A5; + result = 0xA5A5A5A5; + + __asm + ("wrdsp %2\n\t" + "insv %0, %1\n\t" + : "+r"(rt) + : "r"(rs), "r"(dsp) + ); + assert(rt == result); + + return 0; +} |