diff options
author | Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
---|---|---|
committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/cris/check_movmp.s | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/cris/check_movmp.s')
-rw-r--r-- | qemu/tests/tcg/cris/check_movmp.s | 131 |
1 files changed, 131 insertions, 0 deletions
diff --git a/qemu/tests/tcg/cris/check_movmp.s b/qemu/tests/tcg/cris/check_movmp.s new file mode 100644 index 000000000..7fc11f064 --- /dev/null +++ b/qemu/tests/tcg/cris/check_movmp.s @@ -0,0 +1,131 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: ffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n + +# Test generic "move Ps,[]" and "move [],Pd" insns; the ones with +# functionality common to all models. + + .include "testutils.inc" + start + + .data +filler: + .byte 0xaa + .word 0x4433 + .dword 0x55778866 + .byte 0xcc + + .text +; Test that writing to zero-registers is a nop + .if 0 + ; We used to just ignore the writes, but now an error is emitted. We + ; keep the test-code but disabled, in case we need to change this again. + move 0xaa,p0 + move 0x4433,p4 + move 0x55774433,p8 + .endif + + moveq -1,r3 + setf zcvn + clear.b r3 + test_cc 1 1 1 1 + checkr3 ffffff00 + + moveq -1,r3 + clearf zcvn + clear.w r3 + test_cc 0 0 0 0 + checkr3 ffff0000 + + moveq -1,r3 + clear.d r3 + checkr3 0 + +; "Write" using ordinary memory references too. + .if 0 ; See ".if 0" above. + move.d filler,r6 + move [r6],p0 + move [r6],p4 + move [r6],p8 + .endif + +# ffffff00\nffff0000\n0\nffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n + + moveq -1,r3 + clear.b r3 + checkr3 ffffff00 + + moveq -1,r3 + clear.w r3 + checkr3 ffff0000 + + moveq -1,r3 + clear.d r3 + checkr3 0 + +; And postincremented. + .if 0 ; See ".if 0" above. + move [r6+],p0 + move [r6+],p4 + move [r6+],p8 + .endif + +# ffffff00\nffff0000\n0\nbb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n + + moveq -1,r3 + clear.b r3 + checkr3 ffffff00 + + moveq -1,r3 + clear.w r3 + checkr3 ffff0000 + + moveq -1,r3 + clear.d r3 + checkr3 0 + +; Now see that we can write to the registers too. +# bb113344\n664433aa\ncc557788\nabcde012\nabcde000\n77880000\n0\n +; [PC+] + move.d filler,r9 + move 0xbb113344,srp + move srp,r3 + checkr3 bb113344 + +; [R+] + move [r9+],srp + move srp,r3 + checkr3 664433aa + +; [R] + move [r9],srp + move srp,r3 + checkr3 cc557788 + +; And check writing to memory, clear and srp. + + move.d filler,r9 + move 0xabcde012,srp + setf zcvn + move srp,[r9+] + test_cc 1 1 1 1 + subq 4,r9 + move.d [r9],r3 + checkr3 abcde012 + + clearf zcvn + clear.b [r9] + test_cc 0 0 0 0 + move.d [r9],r3 + checkr3 abcde000 + + addq 2,r9 + clear.w [r9+] + subq 2,r9 + move.d [r9],r3 + checkr3 77880000 + + clear.d [r9] + move.d [r9],r3 + checkr3 0 + + quit |