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| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/tests/tcg/cris/check_jsr.s | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/tests/tcg/cris/check_jsr.s')
| -rw-r--r-- | qemu/tests/tcg/cris/check_jsr.s | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/qemu/tests/tcg/cris/check_jsr.s b/qemu/tests/tcg/cris/check_jsr.s new file mode 100644 index 000000000..106023787 --- /dev/null +++ b/qemu/tests/tcg/cris/check_jsr.s @@ -0,0 +1,85 @@ +# mach: crisv3 crisv8 crisv10 crisv32 +# output: 0\n0\n0\n0\n0\n0\n + +# Test that jsr Rn and jsr [PC+] work. + + .include "testutils.inc" + start +x: + move.d 0f,r6 + setf nzvc + jsr r6 + .if 1; ..asm.arch.cris.v32 + nop + .endif +0: + test_move_cc 1 1 1 1 + move srp,r3 + sub.d 0b,r3 + checkr3 0 + + move.d 1f,r0 + setf nzvc + jsr r0 + .if 1 ; ..asm.arch.cris.v32 + moveq 0,r0 + .endif +6: + nop + quit + +2: + test_move_cc 0 0 0 0 + move srp,r3 + sub.d 3f,r3 + checkr3 0 + jsr 4f + .if 1 ; ..asm.arch.cris.v32 + nop + .endif +7: + nop + quit + +8: + move srp,r3 + sub.d 7b,r3 + checkr3 0 + quit + +4: + move srp,r3 + sub.d 7b,r3 + checkr3 0 + move.d 5f,r3 + jump r3 + .if 1; ..asm.arch.cris.v32 + moveq 0,r3 + .endif + quit + + .space 32770,0 +1: + test_move_cc 1 1 1 1 + move srp,r3 + sub.d 6b,r3 + checkr3 0 + + clearf cznv + jsr 2b + .if 1; ..asm.arch.cris.v32 + nop + .endif +3: + + quit + +5: + move srp,r3 + sub.d 7b,r3 + checkr3 0 + jump 8b + .if 1 ; ..asm.arch.cris.v32 + nop + .endif + quit |