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author | Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
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committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/target-sparc/cpu-qom.h | |
parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/target-sparc/cpu-qom.h')
-rw-r--r-- | qemu/target-sparc/cpu-qom.h | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/qemu/target-sparc/cpu-qom.h b/qemu/target-sparc/cpu-qom.h new file mode 100644 index 000000000..477c4d513 --- /dev/null +++ b/qemu/target-sparc/cpu-qom.h @@ -0,0 +1,88 @@ +/* + * QEMU SPARC CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * <http://www.gnu.org/licenses/lgpl-2.1.html> + */ +#ifndef QEMU_SPARC_CPU_QOM_H +#define QEMU_SPARC_CPU_QOM_H + +#include "qom/cpu.h" +#include "cpu.h" + +#ifdef TARGET_SPARC64 +#define TYPE_SPARC_CPU "sparc64-cpu" +#else +#define TYPE_SPARC_CPU "sparc-cpu" +#endif + +#define SPARC_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(SPARCCPUClass, (klass), TYPE_SPARC_CPU) +#define SPARC_CPU(obj) \ + OBJECT_CHECK(SPARCCPU, (obj), TYPE_SPARC_CPU) +#define SPARC_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SPARCCPUClass, (obj), TYPE_SPARC_CPU) + +/** + * SPARCCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_reset: The parent class' reset handler. + * + * A SPARC CPU model. + */ +typedef struct SPARCCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + DeviceRealize parent_realize; + void (*parent_reset)(CPUState *cpu); +} SPARCCPUClass; + +/** + * SPARCCPU: + * @env: #CPUSPARCState + * + * A SPARC CPU. + */ +typedef struct SPARCCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUSPARCState env; +} SPARCCPU; + +static inline SPARCCPU *sparc_env_get_cpu(CPUSPARCState *env) +{ + return container_of(env, SPARCCPU, env); +} + +#define ENV_GET_CPU(e) CPU(sparc_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(SPARCCPU, env) + +void sparc_cpu_do_interrupt(CPUState *cpu); +void sparc_cpu_dump_state(CPUState *cpu, FILE *f, + fprintf_function cpu_fprintf, int flags); +hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +int sparc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, + vaddr addr, int is_write, + int is_user, uintptr_t retaddr); + +#endif |