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| author |   Yang Zhang <yang.z.zhang@intel.com> | 2015-08-28 09:58:54 +0800 |
|---|---|---|
| committer | Yang Zhang <yang.z.zhang@intel.com> | 2015-09-01 12:44:00 +0800 |
| commit | e44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch) | |
| tree | 66b09f592c55df2878107a468a91d21506104d3f /qemu/target-mips/TODO | |
| parent | 9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff) | |
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/target-mips/TODO')
| -rw-r--r-- | qemu/target-mips/TODO | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/qemu/target-mips/TODO b/qemu/target-mips/TODO new file mode 100644 index 000000000..1d782d802 --- /dev/null +++ b/qemu/target-mips/TODO @@ -0,0 +1,51 @@ +Unsolved issues/bugs in the mips/mipsel backend +----------------------------------------------- + +General +------- +- Unimplemented ASEs: + - MDMX + - SmartMIPS + - microMIPS DSP r1 & r2 encodings +- MT ASE only partially implemented and not functional +- Shadow register support only partially implemented, + lacks set switching on interrupt/exception. +- 34K ITC not implemented. +- A general lack of documentation, especially for technical internals. + Existing documentation is x86-centric. +- Reverse endianness bit not implemented +- The TLB emulation is very inefficient: + QEMU's softmmu implements a x86-style MMU, with separate entries + for read/write/execute, a TLB index which is just a modulo of the + virtual address, and a set of TLBs for each user/kernel/supervisor + MMU mode. + MIPS has a single entry for read/write/execute and only one MMU mode. + But it is fully associative with randomized entry indices, and uses + up to 256 ASID tags as additional matching criterion (which roughly + equates to 256 MMU modes). It also has a global flag which causes + entries to match regardless of ASID. + To cope with these differences, QEMU currently flushes the TLB at + each ASID change. Using the MMU modes to implement ASIDs hinges on + implementing the global bit efficiently. +- save/restore of the CPU state is not implemented (see machine.c). + +MIPS64 +------ +- Userland emulation (both n32 and n64) not functional. + +"Generic" 4Kc system emulation +------------------------------ +- Doesn't correspond to any real hardware. Should be removed some day, + U-Boot is the last remaining user. + +PICA 61 system emulation +------------------------ +- No framebuffer support yet. + +MALTA system emulation +---------------------- +- We fake firmware support instead of doing the real thing +- Real firmware (YAMON) falls over when trying to init RAM, presumably + due to lacking system controller emulation. +- Bonito system controller not implemented +- MSC1 system controller not implemented |