diff options
| author |   José Pekkarinen <jose.pekkarinen@nokia.com> | 2016-05-18 13:18:31 +0300 |
|---|---|---|
| committer | José Pekkarinen <jose.pekkarinen@nokia.com> | 2016-05-18 13:42:15 +0300 |
| commit | 437fd90c0250dee670290f9b714253671a990160 (patch) | |
| tree | b871786c360704244a07411c69fb58da9ead4a06 /qemu/target-microblaze/cpu.h | |
| parent | 5bbd6fe9b8bab2a93e548c5a53b032d1939eec05 (diff) | |
These changes are the raw update to qemu-2.6.
Collission happened in the following patches:
migration: do cleanup operation after completion(738df5b9)
Bug fix.(1750c932f86)
kvmclock: add a new function to update env->tsc.(b52baab2)
The code provided by the patches was already in the upstreamed
version.
Change-Id: I3cc11841a6a76ae20887b2e245710199e1ea7f9a
Signed-off-by: José Pekkarinen <jose.pekkarinen@nokia.com>
Diffstat (limited to 'qemu/target-microblaze/cpu.h')
| -rw-r--r-- | qemu/target-microblaze/cpu.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/qemu/target-microblaze/cpu.h b/qemu/target-microblaze/cpu.h index 7e20e59b8..2f7335eaa 100644 --- a/qemu/target-microblaze/cpu.h +++ b/qemu/target-microblaze/cpu.h @@ -19,7 +19,6 @@ #ifndef CPU_MICROBLAZE_H #define CPU_MICROBLAZE_H -#include "config.h" #include "qemu-common.h" #define TARGET_LONG_BITS 32 @@ -34,8 +33,6 @@ typedef struct CPUMBState CPUMBState; #include "mmu.h" #endif -#define ELF_MACHINE EM_MICROBLAZE - #define EXCP_MMU 1 #define EXCP_IRQ 2 #define EXCP_BREAK 3 @@ -297,7 +294,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, #define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model)) #define cpu_exec cpu_mb_exec -#define cpu_gen_code cpu_mb_gen_code #define cpu_signal_handler cpu_mb_signal_handler /* MMU modes definitions */ @@ -309,7 +305,7 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo, #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ -static inline int cpu_mmu_index (CPUMBState *env) +static inline int cpu_mmu_index (CPUMBState *env, bool ifetch) { /* Are we in nommu mode?. */ if (!(env->sregs[SR_MSR] & MSR_VM)) |