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authorYang Zhang <yang.z.zhang@intel.com>2015-08-28 09:58:54 +0800
committerYang Zhang <yang.z.zhang@intel.com>2015-09-01 12:44:00 +0800
commite44e3482bdb4d0ebde2d8b41830ac2cdb07948fb (patch)
tree66b09f592c55df2878107a468a91d21506104d3f /qemu/roms/u-boot/post/board/lwmon5/dsp.c
parent9ca8dbcc65cfc63d6f5ef3312a33184e1d726e00 (diff)
Add qemu 2.4.0
Change-Id: Ic99cbad4b61f8b127b7dc74d04576c0bcbaaf4f5 Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Diffstat (limited to 'qemu/roms/u-boot/post/board/lwmon5/dsp.c')
-rw-r--r--qemu/roms/u-boot/post/board/lwmon5/dsp.c54
1 files changed, 54 insertions, 0 deletions
diff --git a/qemu/roms/u-boot/post/board/lwmon5/dsp.c b/qemu/roms/u-boot/post/board/lwmon5/dsp.c
new file mode 100644
index 000000000..2f55f01ce
--- /dev/null
+++ b/qemu/roms/u-boot/post/board/lwmon5/dsp.c
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
+ *
+ * Developed for DENX Software Engineering GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <post.h>
+
+#if CONFIG_POST & CONFIG_SYS_POST_DSP
+#include <asm/io.h>
+
+/* This test verifies DSP status bits in FPGA */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DSP_STATUS_REG 0xC4000008
+#define FPGA_STATUS_REG 0xC400000C
+
+int dsp_post_test(int flags)
+{
+ uint old_value;
+ uint read_value;
+ int ret;
+
+ /* momorize fpga status */
+ old_value = in_be32((void *)FPGA_STATUS_REG);
+ /* enable outputs */
+ out_be32((void *)FPGA_STATUS_REG, 0x30);
+
+ /* generate sync signal */
+ out_be32((void *)DSP_STATUS_REG, 0x300);
+ udelay(5);
+ out_be32((void *)DSP_STATUS_REG, 0);
+ udelay(500);
+
+ /* read status */
+ ret = 0;
+ read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
+ if (read_value != 0x03) {
+ post_log("\nDSP status read %08X\n", read_value);
+ ret = 1;
+ }
+
+ /* restore fpga status */
+ out_be32((void *)FPGA_STATUS_REG, old_value);
+
+ return ret;
+}
+
+#endif /* CONFIG_POST & CONFIG_SYS_POST_DSP */